Aspeed Ast2500 Datasheet: New
The AST2500 includes an ECC-enabled SPI flash controller. However, the original documentation was ambiguous. The new revision provides explicit code examples for initializing ECC regions for the boot loader. Failure to follow the "new" sequence results in a 30% chance of boot failure after power cycling due to "Flash Uncorrectable Error" flags.
The "new" AST2500 datasheet is interesting because it frequently references the AST2600. Here is how the chips differ according to the latest comparative tables: aspeed ast2500 datasheet new
| Feature | AST2500 (New Datasheet) | AST2600 | | :--- | :--- | :--- | | | ARM9 (32-bit) | ARM11 (64-bit) | | Max DDR Speed | 1600 MT/s | 3200 MT/s | | PCIe Lanes | 1x Gen2 | 2x Gen3 | | MCTP Support | Software-based | Hardware offload | | Die Temperature | Max 105°C | Max 95°C (Tighter limit) | The AST2500 includes an ECC-enabled SPI flash controller
Whether you are debugging an unstable I2C bus, implementing secure boot for medical devices, or simply trying to squeeze 50MHz more performance out of the PCIe bus, the latest revision of the AST2500 datasheet is an indispensable tool. Failure to follow the "new" sequence results in
"The BMC boots fine, but I lose network connectivity after 48 hours." Solution (New Sheet): On page 342 (RMII/RGMII Interface), the new datasheet adds a footnote: "MAC1 auto-negotiation should be disabled if PHY clock drift exceeds 50ppm." The old sheet omitted this.